Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFETs), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. Generally, as illustrated in FIG. 1, a transistor 100 is formed on a portion of a substrate 101 that is separated from other active areas by isolation regions 103. A gate stack 104 includes a gate dielectric 105 and a gate electrode 107. Source/drain extensions 115 are formed using the gate stack 104 as a mask, such that the source/drain extensions 115 are aligned with the gate stack 104. Spacers, such as a first layer of spacers 109 and a second layer of spacers 111 illustrated in FIG. 1, are formed alongside the gate stack 104. The source/drain regions 113 are formed using the first layer of spacers 109, the second layer of spacers 111 and the gate stack 104 as a mask. Current flowing through the source/drain regions 113 may then be controlled by controlling the voltage levels applied to the gate electrode 107.
To increase switching speed and decrease contact resistance, the source/drain regions 113 are often silicided. Typically, the source/drain regions 113, as well as the gate electrode 107, are silicided by forming a metal layer over the source/drain regions 113 and gate electrode 107, and then performing an anneal. The annealing causes the metal layer to react with the silicon substrate, thereby forming a silicide layer 117 on the source/drain regions 113 and the gate electrode 107. The silicide layer 117, however, may cause problems.
One such problem is a parasitic resistance that arises in the source/drain extensions 115. This parasitic resistance degrades the conduction current and lowers the overall efficiency of the transistor.
Therefore, there is a need for a transistor structure and a method of manufacture for a transistor that exhibits low contact resistance as well as reduces the parasitic resistance.